1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more specifically, to a programmable semiconductor integrated circuit configured in a multi-layer structure.
2. Description of Related Art
FIG. 1 shows a configuration of a conventional programmable semiconductor integrated circuit 10 as disclosed in Japanese Patent Laid-Open No. 1994-53689, for example. The semiconductor integrated circuit 10 is provided with CLBs (Configurable Logic Block) 14 containing programmable logic circuits combined with programmable delay circuits such as a flip-flop circuit and PSMs (Programmable Switch Matrix) 12.
FIG. 2 shows a configuration of the PSM 12. The PSM 12 has a plurality of programmable switches 16. Each of the programmable switches 16 switches four wires each other. FIG. 3 shows a configuration of the programmable switch 16. The programmable switch 16 is provided with six switches 18, 20, 22, 24, 26 and 28 for the four wires for example and mutually switches connections among the four signal lines. The semiconductor integrated circuit 10 realizes desirable circuit functions through logical operations of the CLBs 14 and switching operations of the PSMs specified by control signals from the outside.
FIG. 4 is a graph representing the semiconductor integrated circuit 10 having a mesh-type wiring structure. In the semiconductor integrated circuit 10 having the mesh-type wiring structure, a plurality of nodes 30 are connected by wires 32 in mesh. The nodes 30 are the CLBs 14 for example. It is noted that Levels 1, 2, 3 and so on are defined corresponding to the hierarchy of the nodes 30.
Terms are defined as follows, A ‘number of wires’ is a number of wires necessary for constructing a certain type of a graph. For instance, the number of wires in the graph in FIG. 4 is 12. A ‘path’ has a minimum number of interconnected wires necessary for communicating between two nodes. A ‘longest path’ has a route between two nodes wherein the interconnected wires is the longest. ‘Adjacency’ refers to a relationship between two nodes wherein the path is 1. A ‘number of branches’ refers to a number of nodes being able to adjacent to a certain node.
FIGS. 5 and 6 are graphed representations of a semiconductor integrated circuit having a tree-type wiring structure. In the semiconductor integrated circuit having the tree-type wiring structure, a plurality of nodes 34 are connected in a shape of a tree by wires 36. The node 34a may be the PSM for example and the node 34b may be the CLB for example. It is noted that Level 1, 2, 3 and so on are defined corresponding to the hierarchy of the nodes 34 as shown in FIGS. 5 or 6.
In Level 1, there is only one node which is called a root node. A parent-child relationship also exists among the nodes 34 in the semiconductor integrated circuit having the P-branch tree-type wiring structure. That is, the nodes on Level (L) are adjacent to the parent node, which is the node on Level (L−1), and to the P-child nodes, which are the nodes on Level (L+1).
FIG. 7 is a graph showing the relationship between the number of nodes N and the number of wires of the mesh-type and tree-type wiring structures. The number of nodes on Level (L) is L2 in case of the mesh-type and PL−1 in case of the P-branch tree-type wiring structure. The number of wires on Level (L) is 2L(L−1) in case of the mesh-type and is PL−1 in case of the P-branch tree-type wiring structure. Accordingly, although the number of wires of the mesh-type wiring structure is almost equal to that of the binary tree-type wiring structure provided that the number of nodes are equal. The more the number of branches increases from the parent node like a quarter tree-type and octal tree-type wiring structures, the less the number of wires becomes as shown in FIG. 7.
FIG. 8 is a graph showing the relationship between the number of nodes N and the longest path in the mesh-type and tree-type wiring structures. The number of nodes on Level (L) is L2 in case of the mesh-type wiring structure and is PL−1 in case of the P-branch tree-type wiring structure. Still more, the longest path on Level (L) is 2(L−1) in case of the mesh-type wiring structure and 2(L−1) in case of the P-branch tree-type wiring structure. Accordingly, when the number of nodes N becomes 40 is more, the longest path of any one of the binary tree-type, quarter tree-type and octal tree-type wiring structures becomes smaller than that of the mesh-type wiring structure as shown in FIG. 8.
As described above, the tree-type wiring structure is advantageous over the mesh-type wiring structure from the both aspects of the number of wires and the longest path. Still more, the larger the number of branches of the tree-type wiring structure, the more advantageous over the mesh-type wiring structure becomes.
FIG. 9 is a schematic plan view of the PSM having eight input/outputs. The eight-input/outputs PSM is provided with 28 MOSFETs as switches to eight signal lines and mutually switches connections among the eight signal lines. Therefore, because the MOSFETs are integrated in a plane of a single semiconductor layer in the conventional semiconductor integrated circuit, there has been a problem that a circuit area becomes very large in implementing a complicated circuit by using a large number of MOSFETs. Accordingly, although the tree-type wiring structure is advantageous over the mesh-type wiring structure and is more advantageous if the number of branches is large as described above, it has been difficult to realize it from the aspect that the circuit area becomes very large.
Accordingly, it is an object of the invention to provide a semiconductor integrated circuit which is capable of solving the above-mentioned problem. This object may be achieved through the combination of features described in independent claims of the invention. Dependent claims thereof specify preferable embodiments of the invention.